1. Field of Use
The present invention relates to the cooperative operation of multiple processors in a single system and, more particularly, to a means for reducing the number of interrupt retry attempts between processors of a system.
2. Prior Art
A recurring problem in present computer systems arises from the need to combine the various processors of a multiple processor system into a cooperative system, and in particular to the need to integrate communications between the processors of a system.
This problem frequently occurs in coordinating the operations of the interrupt mechanisms of the processors of the system. As is well known, "interrupts" are a primary means of communication between the elements of most computer systems, whereby one element of the system, such as a processor or peripheral device, hereinafter generally referred to as a "processor", may send a request, referred to as an "interrupt", to another element of the system, such as another processor or peripheral device, hereinafter also generally referred to as a "processor", requesting that the other element of the system perform some operation for the requesting element. Interrupts are commonly assigned priority levels and, if the processor receiving the interrupt is executing an operation or servicing an interrupt of lower priority level than the interrupt, the receiving processor will suspend, or interrupt, the current operation and perform the action requested by the interrupt. If, however, the receiving processor is servicing an interrupt of a high priority than the new request, the new request will be denied, commonly referred to as "not acknowledge", and the requesting processor must repeat the request for the interrupt at a later tie, and must generally continue to repeat the interrupt request until the request is accepted. The repetition of interrupt requests until accepted, however, can consume substantial amounts of processor and system bus resources that are urgently needed for actual operations.
This problem arises both in system using a single type of processor and, even more acutely, in systems using different types of processor units in a single system to allow the system of perform a wider range of operations than may be achieved through a system using a single type of processor or to increase the performance of the system by adding faster and more powerful processors or processors providing special capabilities.
The requirement for a multiple processor type system may arise, for example, from a requirement to provide a system which is capable of operating with both the application programs and user data files created for an installed, proprietary system and the new "industry standard", or "open system", operating systems and application programs. Such hybrid systems are becoming more common as the need increases in the computer industry to provide systems which allow a user which has a very large installed proprietary system base to "migrate" over time to the presently proposed "open systems" which use "industry standard" hardware and one of the "industry standard" operating systems. An example of such would be the combination of one of the present "industry standard" processor units, such as an Intel.sup.1 80486.sup.2 microprocessor running the UNIX.sup.3 operating system and compatible applications programs, into a system based upon a proprietary operating system and hardware, such as the DPS 6000.sup.4 computer system available from Bull HN Information Systems Inc., which runs applications programs designed for the proprietary system. It is possible, in such a hybrid system, for one of the processor types to have some form of interrupt coordination communication among themselves, but for the other processor type to either have no form of interrupt coordination communication or to have a form of interrupt coordination communication which is not compatible with that of the first type of processors. FNT .sup.1 Intel is a trademark of Intel Corporation. FNT .sup.2 i486 is a trademark of Intel Corporation. FNT .sup.3 Unix is a trademark of UNIX System Laboratories Inc. FNT .sup.4 DPS and DPS6000 are trademarks of Bull NH Informations Systems Inc.
It is also well known, and a further problem in interrupt communication between processors, that different types of processors frequently recognize and use different types, numbers and levels of interrupts, so that communication between, for example, a peripheral device designed for a proprietary system such as a DPS 6000 and a processor such as the Intel 80486, are very difficult.
It is therefore an object of the present invention to provide a solution to this and other related problems in marrying, or interfacing, the interrupt mechanisms of different types of processors into a single, cooperative system.